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Parallel computing

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</style><div role="note" class="hatnote navigation-not-searchable">"Parallelization" redirects here. For parallelization of manifolds, see <a href="Parallelization_(mathematics)" title="Parallelization (mathematics)">Parallelization (mathematics)</a>.</div>

Parallel computing is a type of <a href="Computing" title="Computing">computation</a> in which many calculations or <a href="Process_(computing)" title="Process (computing)">processes</a> are carried out simultaneously.<a href="#cite_note-1">[1]</a> Large problems can often be divided into smaller ones, which can then be solved at the same time. There are several different forms of parallel computing: <a href="Bit-level_parallelism" title="Bit-level parallelism">bit-level</a>, <a href="Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level</a>, <a href="Data_parallelism" title="Data parallelism">data</a>, and <a href="Task_parallelism" title="Task parallelism">task parallelism</a>. Parallelism has long been employed in <a href="High-performance_computing" title="High-performance computing">high-performance computing</a>, but has gained broader interest due to the physical constraints preventing <a href="Frequency_scaling" title="Frequency scaling">frequency scaling</a>.<a href="#cite_note-:0-2">[2]</a> As power consumption (and consequently heat generation) by computers has become a concern in recent years,<a href="#cite_note-3">[3]</a> parallel computing has become the dominant paradigm in <a href="Computer_architecture" title="Computer architecture">computer architecture</a>, mainly in the form of <a href="Multi-core_processor" title="Multi-core processor">multi-core processors</a>.<a href="#cite_note-View-Power-4">[4]</a>

In <a href="Computer_science" title="Computer science">computer science</a>, parallelism and concurrency are two different things: a parallel program uses <a href="Multi-core_processor" title="Multi-core processor">multiple CPU cores</a>, each core performing a task independently. On the other hand, concurrency enables a program to deal with multiple tasks even on a single CPU core; the core switches between tasks (i.e. <a href="Thread_(computing)" title="Thread (computing)">threads</a>) without necessarily completing each one. A program can have both, neither or a combination of parallelism and concurrency characteristics.<a href="#cite_note-5">[5]</a>

Parallel computers can be roughly classified according to the level at which the hardware supports parallelism, with multi-core and <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">multi-processor</a> computers having multiple <a href="Processing_element" class="mw-redirect" title="Processing element">processing elements</a> within a single machine, while <a href="Computer_cluster" title="Computer cluster">clusters</a>, <a href="Massively_parallel_(computing)" class="mw-redirect" title="Massively parallel (computing)">MPPs</a>, and <a href="Grid_computing" title="Grid computing">grids</a> use multiple computers to work on the same task. Specialized parallel computer architectures are sometimes used alongside traditional processors, for accelerating specific tasks.

In some cases parallelism is transparent to the programmer, such as in bit-level or instruction-level parallelism, but explicitly <a href="Parallel_algorithm" title="Parallel algorithm">parallel algorithms</a>, particularly those that use concurrency, are more difficult to write than <a href="Sequential_algorithm" title="Sequential algorithm">sequential</a> ones,<a href="#cite_note-6">[6]</a> because concurrency introduces several new classes of potential <a href="Software_bug" title="Software bug">software bugs</a>, of which <a href="Race_condition" title="Race condition">race conditions</a> are the most common. <a href="Computer_networking" class="mw-redirect" title="Computer networking">Communication</a> and <a href="Synchronization_(computer_science)" title="Synchronization (computer science)">synchronization</a> between the different subtasks are typically some of the greatest obstacles to getting optimal parallel program performance.

A theoretical <a href="Upper_bound" class="mw-redirect" title="Upper bound">upper bound</a> on the <a href="Speedup" title="Speedup">speed-up</a> of a single program as a result of parallelization is given by <a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a>, which states that it is limited by the fraction of time for which the parallelization can be utilised.

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<div class="mw-heading mw-heading2"><h2 id="Background">Background</h2></div>

Traditionally, <a href="Computer_software" class="mw-redirect" title="Computer software">computer software</a> has been written for <a href="Serial_computation" class="mw-redirect" title="Serial computation">serial computation</a>. To solve a problem, an <a href="Algorithm" title="Algorithm">algorithm</a> is constructed and implemented as a serial stream of instructions. These instructions are executed on a <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> on one computer. Only one instruction may execute at a time—after that instruction is finished, the next one is executed.<a href="#cite_note-llnltut-7">[7]</a>

Parallel computing, on the other hand, uses multiple processing elements simultaneously to solve a problem. This is accomplished by breaking the problem into independent parts so that each processing element can execute its part of the algorithm simultaneously with the others. The processing elements can be diverse and include resources such as a single computer with multiple processors, several networked computers, specialized hardware, or any combination of the above.<a href="#cite_note-llnltut-7">[7]</a> Historically parallel computing was used for scientific computing and the simulation of scientific problems, particularly in the natural and <a href="Engineering_sciences" class="mw-redirect" title="Engineering sciences">engineering sciences</a>, such as <a href="Meteorology" title="Meteorology">meteorology</a>. This led to the design of parallel hardware and software, as well as <a href="High_performance_computing" class="mw-redirect" title="High performance computing">high performance computing</a>.<a href="#cite_note-8">[8]</a>

<a href="Frequency_scaling" title="Frequency scaling">Frequency scaling</a> was the dominant reason for improvements in <a href="Computer_performance" title="Computer performance">computer performance</a> from the mid-1980s until 2004. The <a href="Run_time_(program_lifecycle_phase)" class="mw-redirect" title="Run time (program lifecycle phase)">runtime</a> of a program is equal to the number of instructions multiplied by the average time per instruction. Maintaining everything else constant, increasing the clock frequency decreases the average time it takes to execute an instruction. An increase in frequency thus decreases runtime for all <a href="CPU_bound" class="mw-redirect" title="CPU bound">compute-bound</a> programs.<a href="#cite_note-9">[9]</a> However, power consumption P by a chip is given by the equation P = C × V 2 × F, where C is the <a href="Capacitance" title="Capacitance">capacitance</a> being switched per clock cycle (proportional to the number of transistors whose inputs change), V is <a href="Voltage" title="Voltage">voltage</a>, and F is the processor frequency (cycles per second).<a href="#cite_note-10">[10]</a> Increases in frequency increase the amount of power used in a processor. Increasing processor power consumption led ultimately to <a href="Intel" title="Intel">Intel</a>'s May 8, 2004 cancellation of its <a href="Tejas_and_Jayhawk" title="Tejas and Jayhawk">Tejas and Jayhawk</a> processors, which is generally cited as the end of frequency scaling as the dominant computer architecture paradigm.<a href="#cite_note-11">[11]</a>

To deal with the problem of power consumption and overheating the major <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU or processor) manufacturers started to produce power efficient processors with multiple cores. The core is the computing unit of the processor and in multi-core processors each core is independent and can access the same memory concurrently. <a href="Multi-core_processor" title="Multi-core processor">Multi-core processors</a> have brought parallel computing to <a href="Desktop_computers" class="mw-redirect" title="Desktop computers">desktop computers</a>. Thus parallelization of serial programs has become a mainstream programming task. In 2012 quad-core processors became standard for <a href="Desktop_computers" class="mw-redirect" title="Desktop computers">desktop computers</a>, while <a href="Server_(computing)" title="Server (computing)">servers</a> had 10+ core processors. By 2023 some processors had over hundred cores. Some designs having a mix of performance and efficiency cores (such as <a href="ARM_big.LITTLE" title="ARM big.LITTLE">ARM's big.LITTLE</a> design) due to thermal and design constraints.<a href="#cite_note-12">[12]</a> From <a href="Moore's_law" title="Moore's law">Moore's law</a> it can be predicted that the number of cores per processor will double every 18–24 months.

An <a href="Operating_system" title="Operating system">operating system</a> can ensure that different tasks and user programs are run in parallel on the available cores. However, for a serial software program to take full advantage of the multi-core architecture the programmer needs to restructure and parallelize the code. A speed-up of application software runtime will no longer be achieved through frequency scaling, instead programmers will need to parallelize their software code to take advantage of the increasing computing power of multicore architectures.<a href="#cite_note-13">[13]</a>

<div class="mw-heading mw-heading3"><h3 id="Relevant_laws">Relevant laws</h3></div>

Main article: <a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a>

Optimally, the <a href="Speedup" title="Speedup">speedup</a> from parallelization would be linear—doubling the number of processing elements should halve the runtime, and doubling it a second time should again halve the runtime. However, very few parallel algorithms achieve optimal speedup. Most of them have a near-linear speedup for small numbers of processing elements, which flattens out into a constant value for large numbers of processing elements.

The maximum potential speedup of an overall system can be calculated by <a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a>.<a href="#cite_note-:02-14">[14]</a> Amdahl's Law indicates that optimal performance improvement is achieved by balancing enhancements to both parallelizable and non-parallelizable components of a task. Furthermore, it reveals that increasing the number of processors yields diminishing returns, with negligible speedup gains beyond a certain point. <a href="#cite_note-15">[15]</a><a href="#cite_note-16">[16]</a>

Amdahl's Law has limitations, including assumptions of fixed workload, neglecting <a href="Inter-process_communication" title="Inter-process communication">inter-process communication</a> and <a href="Synchronization_(computer_science)" title="Synchronization (computer science)">synchronization</a> overheads, primarily focusing on computational aspect and ignoring extrinsic factors such as data persistence, I/O operations, and memory access overheads.<a href="#cite_note-17">[17]</a><a href="#cite_note-:1-18">[18]</a><a href="#cite_note-19">[19]</a>

<a href="Gustafson's_law" title="Gustafson's law">Gustafson's law</a> and <a href="Neil_J._Gunther#Universal_Scalability_Law" title="Neil J. Gunther">Universal Scalability Law</a> give a more realistic assessment of the parallel performance.<a href="#cite_note-20">[20]</a><a href="#cite_note-21">[21]</a>

<div class="mw-heading mw-heading3"><h3 id="Dependencies">Dependencies</h3></div>

Understanding <a href="Data_dependency" title="Data dependency">data dependencies</a> is fundamental in implementing <a href="Parallel_algorithm" title="Parallel algorithm">parallel algorithms</a>. No program can run more quickly than the longest chain of dependent calculations (known as the <a href="Critical_path_method" title="Critical path method">critical path</a>), since calculations that depend upon prior calculations in the chain must be executed in order. However, most algorithms do not consist of just a long chain of dependent calculations; there are usually opportunities to execute independent calculations in parallel.

Let Pi and Pj be two program segments. Bernstein's conditions<a href="#cite_note-22">[22]</a> describe when the two are independent and can be executed in parallel. For Pi, let Ii be all of the input variables and Oi the output variables, and likewise for Pj. Pi and Pj are independent if they satisfy

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<annotation encoding="application/x-tex">{\displaystyle I_{j}\cap O_{i}=\varnothing ,}</annotation>

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</math><img src="./1d0dcfecb17d55baca48e4eaba2b2182f7fbc971.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.005ex; width:12.642ex; height:2.843ex;" alt="{\displaystyle I_{j}\cap O_{i}=\varnothing ,}" loading="lazy"></dd>

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<annotation encoding="application/x-tex">{\displaystyle I_{i}\cap O_{j}=\varnothing ,}</annotation>

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</math><img src="./e07eb3cfaf6b5930579d0616b7a5b93bd23ef216.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.005ex; width:12.642ex; height:2.843ex;" alt="{\displaystyle I_{i}\cap O_{j}=\varnothing ,}" loading="lazy"></dd>

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<annotation encoding="application/x-tex">{\displaystyle O_{i}\cap O_{j}=\varnothing .}</annotation>

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</math><img src="./8f88a5f909aa03587600d57e1475bc51419bfaeb.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.005ex; width:13.392ex; height:2.843ex;" alt="{\displaystyle O_{i}\cap O_{j}=\varnothing .}" loading="lazy"></dd></dl>

Violation of the first condition introduces a flow dependency, corresponding to the first segment producing a result used by the second segment. The second condition represents an anti-dependency, when the second segment produces a variable needed by the first segment. The third and final condition represents an output dependency: when two segments write to the same location, the result comes from the logically last executed segment.<a href="#cite_note-23">[23]</a>

Consider the following functions, which demonstrate several kinds of dependencies:

<pre>1: function Dep(a, b)

2: c := a * b

3: d := 3 * c

4: end function

</pre>

In this example, instruction 3 cannot be executed before (or even in parallel with) instruction 2, because instruction 3 uses a result from instruction 2. It violates condition 1, and thus introduces a flow dependency.

<pre>1: function NoDep(a, b)

2: c := a * b

3: d := 3 * b

4: e := a + b

5: end function

</pre>

In this example, there are no dependencies between the instructions, so they can all be run in parallel.

Bernstein's conditions do not allow memory to be shared between different processes. For that, some means of enforcing an ordering between accesses is necessary, such as <a href="Semaphore_(programming)" title="Semaphore (programming)">semaphores</a>, <a href="Barrier_(computer_science)" title="Barrier (computer science)">barriers</a> or some other <a href="Synchronization_(computer_science)" title="Synchronization (computer science)">synchronization method</a>.

<div class="mw-heading mw-heading3"><h3 id="Race_conditions,_mutual_exclusion,_synchronization,_and_parallel_slowdown">Race conditions, mutual exclusion, synchronization, and parallel slowdown</h3></div>

Subtasks in a parallel program are often called <a href="Thread_(computing)" title="Thread (computing)">threads</a>. Some parallel computer architectures use smaller, lightweight versions of threads known as <a href="Fiber_(computer_science)" title="Fiber (computer science)">fibers</a>, while others use bigger versions known as <a href="Process_(computing)" title="Process (computing)">processes</a>. However, "threads" is generally accepted as a generic term for subtasks.<a href="#cite_note-24">[24]</a> Threads will often need <a href="Synchronization_(computer_science)" title="Synchronization (computer science)">synchronized</a> access to an <a href="Object_(computer_science)" title="Object (computer science)">object</a> or other <a href="Resource_management_(computing)" title="Resource management (computing)">resource</a>, for example when they must update a <a href="Variable_(programming)" class="mw-redirect" title="Variable (programming)">variable</a> that is shared between them. Without synchronization, the instructions between the two threads may be interleaved in any order. For example, consider the following program:

<th>Thread A

</th>

<th>Thread B

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<tr>

<td>1A: Read variable V

</td>

<td>1B: Read variable V

</td></tr>

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<td>2A: Add 1 to variable V

</td>

<td>2B: Add 1 to variable V

</td></tr>

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<td>3A: Write back to variable V

</td>

<td>3B: Write back to variable V

</td></tr></tbody></table>

If instruction 1B is executed between 1A and 3A, or if instruction 1A is executed between 1B and 3B, the program will produce incorrect data. This is known as a <a href="Race_condition" title="Race condition">race condition</a>. The programmer must use a <a href="Lock_(computer_science)" title="Lock (computer science)">lock</a> to provide <a href="Mutual_exclusion" title="Mutual exclusion">mutual exclusion</a>. A lock is a programming language construct that allows one thread to take control of a variable and prevent other threads from reading or writing it, until that variable is unlocked. The thread holding the lock is free to execute its <a href="Critical_section" title="Critical section">critical section</a> (the section of a program that requires exclusive access to some variable), and to unlock the data when it is finished. Therefore, to guarantee correct program execution, the above program can be rewritten to use locks:

<th>Thread A

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<th>Thread B

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<tr>

<td>1A: Lock variable V

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<td>1B: Lock variable V

</td></tr>

<tr>

<td>2A: Read variable V

</td>

<td>2B: Read variable V

</td></tr>

<tr>

<td>3A: Add 1 to variable V

</td>

<td>3B: Add 1 to variable V

</td></tr>

<tr>

<td>4A: Write back to variable V

</td>

<td>4B: Write back to variable V

</td></tr>

<tr>

<td>5A: Unlock variable V

</td>

<td>5B: Unlock variable V

</td></tr></tbody></table>

One thread will successfully lock variable V, while the other thread will be <a href="Software_lockout" title="Software lockout">locked out</a>—unable to proceed until V is unlocked again. This guarantees correct execution of the program. Locks may be necessary to ensure correct program execution when threads must serialize access to resources, but their use can greatly slow a program and may affect its <a href="Software_quality#Reliability" title="Software quality">reliability</a>.<a href="#cite_note-25">[25]</a>

Locking multiple variables using <a href="Atomic_operation" class="mw-redirect" title="Atomic operation">non-atomic</a> locks introduces the possibility of program <a href="Deadlock_(computer_science)" title="Deadlock (computer science)">deadlock</a>. An <a href="Atomic_lock" class="mw-redirect" title="Atomic lock">atomic lock</a> locks multiple variables all at once. If it cannot lock all of them, it does not lock any of them. If two threads each need to lock the same two variables using non-atomic locks, it is possible that one thread will lock one of them and the second thread will lock the second variable. In such a case, neither thread can complete, and deadlock results.<a href="#cite_note-26">[26]</a>

Many parallel programs require that their subtasks <a href="Synchronization_(computer_science)" title="Synchronization (computer science)">act in synchrony</a>. This requires the use of a <a href="Barrier_(computer_science)" title="Barrier (computer science)">barrier</a>. Barriers are typically implemented using a lock or a <a href="Semaphore_(programming)" title="Semaphore (programming)">semaphore</a>.<a href="#cite_note-27">[27]</a> One class of algorithms, known as <a href="Lock-free_and_wait-free_algorithms" class="mw-redirect" title="Lock-free and wait-free algorithms">lock-free and wait-free algorithms</a>, altogether avoids the use of locks and barriers. However, this approach is generally difficult to implement and requires correctly designed data structures.<a href="#cite_note-28">[28]</a>

Not all parallelization results in speed-up. Generally, as a task is split up into more and more threads, those threads spend an ever-increasing portion of their time communicating with each other or waiting on each other for access to resources.<a href="#cite_note-29">[29]</a><a href="#cite_note-30">[30]</a> Once the overhead from resource contention or communication dominates the time spent on other computation, further parallelization (that is, splitting the workload over even more threads) increases rather than decreases the amount of time required to finish. This problem, known as <a href="Parallel_slowdown" title="Parallel slowdown">parallel slowdown</a>,<a href="#cite_note-31">[31]</a> can be improved in some cases by software analysis and redesign.<a href="#cite_note-32">[32]</a>

<div class="mw-heading mw-heading3"><h3 id="Fine-grained,_coarse-grained,_and_embarrassing_parallelism">Fine-grained, coarse-grained, and embarrassing parallelism</h3></div>

Applications are often classified according to how often their subtasks need to synchronize or communicate with each other. An application exhibits fine-grained parallelism if its subtasks must communicate many times per second; it exhibits coarse-grained parallelism if they do not communicate many times per second, and it exhibits <a href="Embarrassingly_parallel" title="Embarrassingly parallel">embarrassing parallelism</a> if they rarely or never have to communicate. Embarrassingly parallel applications are considered the easiest to parallelize.

<div class="mw-heading mw-heading3"><h3 id="Flynn's_taxonomy">Flynn's taxonomy</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></div>

<a href="Michael_J._Flynn" title="Michael J. Flynn">Michael J. Flynn</a> created one of the earliest classification systems for parallel (and sequential) computers and programs, now known as <a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a>. Flynn classified programs and computers by whether they were operating using a single set or multiple sets of instructions, and whether or not those instructions were using a single set or multiple sets of data.

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</style><table class="sidebar nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th></tr><tr><th class="sidebar-heading">

Single data stream</th></tr><tr><td class="sidebar-content">

</tr><tr><th class="sidebar-heading">

Multiple data streams</th></tr><tr><td class="sidebar-content">

</tr><tr><th class="sidebar-heading">

SIMD subcategories<a href="#cite_note-flynn-1972-33">[33]</a></th></tr><tr><td class="sidebar-content">

<ul><li><a href="Flynn's_taxonomy#Array_processor" title="Flynn's taxonomy">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing (packed SIMD)</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing (predicated/masked SIMD)</a></li></ul></td>

</tr><tr><th class="sidebar-heading">

See also</th></tr><tr><td class="sidebar-content">

</tr></tbody></table>

The single-instruction-single-data (SISD) classification is equivalent to an entirely sequential program. The single-instruction-multiple-data (SIMD) classification is analogous to doing the same operation repeatedly over a large data set. This is commonly done in <a href="Signal_processing" title="Signal processing">signal processing</a> applications. Multiple-instruction-single-data (MISD) is a rarely used classification. While computer architectures to deal with this were devised (such as <a href="Systolic_array" title="Systolic array">systolic arrays</a>), few applications that fit this class materialized. Multiple-instruction-multiple-data (MIMD) programs are by far the most common type of parallel programs.

According to <a href="David_A._Patterson_(scientist)" class="mw-redirect" title="David A. Patterson (scientist)">David A. Patterson</a> and <a href="John_L._Hennessy" title="John L. Hennessy">John L. Hennessy</a>, "Some machines are hybrids of these categories, of course, but this classic model has survived because it is simple, easy to understand, and gives a good first approximation. It is also—perhaps because of its understandability—the most widely used scheme."<a href="#cite_note-34">[34]</a>

<div class="mw-heading mw-heading2"><h2 id="Disadvantages">Disadvantages</h2></div>

Parallel computing can incur significant overhead in practice, primarily due to the costs associated with merging data from multiple processes. Specifically, inter-process communication and synchronization can lead to overheads that are substantially higher—often by two or more orders of magnitude—compared to processing the same data on a single thread. <a href="#cite_note-35">[35]</a><a href="#cite_note-36">[36]</a><a href="#cite_note-37">[37]</a> Therefore, the overall improvement should be carefully evaluated.

<div class="mw-heading mw-heading2"><h2 id="Granularity">Granularity</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Bit-level_parallelism">Bit-level parallelism</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Bit-level_parallelism" title="Bit-level parallelism">Bit-level parallelism</a></div>

From the advent of <a href="Very-large-scale_integration" title="Very-large-scale integration">very-large-scale integration</a> (VLSI) computer-chip fabrication technology in the 1970s until about 1986, speed-up in computer architecture was driven by doubling <a href="Word_(data_type)" class="mw-redirect" title="Word (data type)">computer word size</a>—the amount of information the processor can manipulate per cycle.<a href="#cite_note-38">[38]</a> Increasing the word size reduces the number of instructions the processor must execute to perform an operation on variables whose sizes are greater than the length of the word. For example, where an <a href="8-bit_computing" title="8-bit computing">8-bit</a> processor must add two <a href="16-bit_computing" title="16-bit computing">16-bit</a> <a href="Integer" title="Integer">integers</a>, the processor must first add the 8 lower-order bits from each integer using the standard addition instruction, then add the 8 higher-order bits using an add-with-carry instruction and the <a href="Carry_bit" class="mw-redirect" title="Carry bit">carry bit</a> from the lower order addition; thus, an 8-bit processor requires two instructions to complete a single operation, where a 16-bit processor would be able to complete the operation with a single instruction.

Historically, <a href="4-bit_computing" title="4-bit computing">4-bit</a> microprocessors were replaced with 8-bit, then 16-bit, then 32-bit microprocessors. This trend generally came to an end with the introduction of 32-bit processors, which has been a standard in general-purpose computing for two decades. Not until the early 2000s, with the advent of <a href="X86-64" title="X86-64">x86-64</a> architectures, did <a href="64-bit_computing" title="64-bit computing">64-bit</a> processors become commonplace.

<div class="mw-heading mw-heading3"><h3 id="Instruction-level_parallelism">Instruction-level parallelism</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction-level parallelism</a></div>

A computer program is, in essence, a stream of instructions executed by a processor. Without instruction-level parallelism, a processor can only issue less than one <a href="Instructions_per_cycle" title="Instructions per cycle">instruction per clock cycle</a> (IPC < 1). These processors are known as subscalar processors. These instructions can be <a href="Out-of-order_execution" title="Out-of-order execution">re-ordered</a> and combined into groups which are then executed in parallel without changing the result of the program. This is known as instruction-level parallelism. Advances in instruction-level parallelism dominated computer architecture from the mid-1980s until the mid-1990s.<a href="#cite_note-39">[39]</a>

All modern processors have multi-stage <a href="Instruction_pipelining" title="Instruction pipelining">instruction pipelines</a>. Each stage in the pipeline corresponds to a different action the processor performs on that instruction in that stage; a processor with an N-stage pipeline can have up to N different instructions at different stages of completion and thus can issue one instruction per clock cycle (IPC = 1). These processors are known as scalar processors. The canonical example of a pipelined processor is a <a href="RISC" class="mw-redirect" title="RISC">RISC</a> processor, with five stages: instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and register write back (WB). The <a href="Pentium_4" title="Pentium 4">Pentium 4</a> processor had a 35-stage pipeline.<a href="#cite_note-40">[40]</a>

Most modern processors also have multiple <a href="Execution_unit" title="Execution unit">execution units</a>. They usually combine this feature with pipelining and thus can issue more than one instruction per clock cycle (IPC > 1). These processors are known as <a href="Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> processors. Superscalar processors differ from <a href="Multi-core_processor" title="Multi-core processor">multi-core processors</a> in that the several execution units are not entire processors (i.e. processing units). Instructions can be grouped together only if there is no <a href="Data_dependency" title="Data dependency">data dependency</a> between them. <a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a> and the <a href="Tomasulo_algorithm" class="mw-redirect" title="Tomasulo algorithm">Tomasulo algorithm</a> (which is similar to scoreboarding but makes use of <a href="Register_renaming" title="Register renaming">register renaming</a>) are two of the most common techniques for implementing out-of-order execution and instruction-level parallelism.

<div class="mw-heading mw-heading3"><h3 id="Task_parallelism">Task parallelism</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Task_parallelism" title="Task parallelism">Task parallelism</a></div>

Task parallelisms is the characteristic of a parallel program that "entirely different calculations can be performed on either the same or different sets of data".<a href="#cite_note-Culler124-41">[41]</a> This contrasts with data parallelism, where the same calculation is performed on the same or different sets of data. Task parallelism involves the decomposition of a task into sub-tasks and then allocating each sub-task to a processor for execution. The processors would then execute these sub-tasks concurrently and often cooperatively. Task parallelism does not usually scale with the size of a problem.<a href="#cite_note-Culler125-42">[42]</a>

<div class="mw-heading mw-heading3"><h3 id="Superword_level_parallelism">Superword level parallelism</h3></div>

Superword level parallelism is a <a href="Automatic_vectorization" title="Automatic vectorization">vectorization</a> technique based on <a href="Loop_unwinding" class="mw-redirect" title="Loop unwinding">loop unrolling</a> and basic block vectorization. It is distinct from loop vectorization algorithms in that it can exploit <a href="Parallelism_(computing)" class="mw-redirect" title="Parallelism (computing)">parallelism</a> of <a href="Inline_code" class="mw-redirect" title="Inline code">inline code</a>, such as manipulating coordinates, color channels or in loops unrolled by hand.<a href="#cite_note-43">[43]</a>

<div class="mw-heading mw-heading2"><h2 id="Hardware">Hardware</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Memory_and_communication">Memory and communication</h3></div>

Main memory in a parallel computer is either <a href="Shared_memory_(interprocess_communication)" class="mw-redirect" title="Shared memory (interprocess communication)">shared memory</a> (shared between all processing elements in a single <a href="Address_space" title="Address space">address space</a>), or <a href="Distributed_memory" title="Distributed memory">distributed memory</a> (in which each processing element has its own local address space).<a href="#cite_note-PH713-44">[44]</a> Distributed memory refers to the fact that the memory is logically distributed, but often implies that it is physically distributed as well. <a href="Distributed_shared_memory" title="Distributed shared memory">Distributed shared memory</a> and <a href="Memory_virtualization" title="Memory virtualization">memory virtualization</a> combine the two approaches, where the processing element has its own local memory and access to the memory on non-local processors. Accesses to local memory are typically faster than accesses to non-local memory. On the <a href="Supercomputers" class="mw-redirect" title="Supercomputers">supercomputers</a>, distributed shared memory space can be implemented using the programming model such as <a href="Partitioned_global_address_space" title="Partitioned global address space">PGAS</a>. This model allows processes on one compute node to transparently access the remote memory of another compute node. All compute nodes are also connected to an external shared memory system via high-speed interconnect, such as <a href="Infiniband" class="mw-redirect" title="Infiniband">Infiniband</a>, this external shared memory system is known as <a href="Burst_buffer" title="Burst buffer">burst buffer</a>, which is typically built from arrays of <a href="Non-volatile_memory" title="Non-volatile memory">non-volatile memory</a> physically distributed across multiple I/O nodes.

Computer architectures in which each element of main memory can be accessed with equal <a href="Memory_latency" title="Memory latency">latency</a> and <a href="Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> are known as <a href="Uniform_memory_access" title="Uniform memory access">uniform memory access</a> (UMA) systems. Typically, that can be achieved only by a <a href="Shared_memory_(interprocess_communication)" class="mw-redirect" title="Shared memory (interprocess communication)">shared memory</a> system, in which the memory is not physically distributed. A system that does not have this property is known as a <a href="Non-uniform_memory_access" title="Non-uniform memory access">non-uniform memory access</a> (NUMA) architecture. Distributed memory systems have non-uniform memory access.

Computer systems make use of <a href="CPU_cache" title="CPU cache">caches</a>—small and fast memories located close to the processor which store temporary copies of memory values (nearby in both the physical and logical sense). Parallel computer systems have difficulties with caches that may store the same value in more than one location, with the possibility of incorrect program execution. These computers require a <a href="Cache_coherency" class="mw-redirect" title="Cache coherency">cache coherency</a> system, which keeps track of cached values and strategically purges them, thus ensuring correct program execution. <a href="Bus_sniffing" class="mw-redirect" title="Bus sniffing">Bus snooping</a> is one of the most common methods for keeping track of which values are being accessed (and thus should be purged). Designing large, high-performance cache coherence systems is a very difficult problem in computer architecture. As a result, shared memory computer architectures do not scale as well as distributed memory systems do.<a href="#cite_note-PH713-44">[44]</a>

Processor–processor and processor–memory communication can be implemented in hardware in several ways, including via shared (either multiported or <a href="Multiplexing" title="Multiplexing">multiplexed</a>) memory, a <a href="Crossbar_switch" title="Crossbar switch">crossbar switch</a>, a shared <a href="Bus_(computing)" title="Bus (computing)">bus</a> or an interconnect network of a myriad of <a href="Network_topology" title="Network topology">topologies</a> including <a href="Star_network" title="Star network">star</a>, <a href="Ring_network" title="Ring network">ring</a>, <a href="Tree_(graph_theory)" title="Tree (graph theory)">tree</a>, <a href="Hypercube_graph" title="Hypercube graph">hypercube</a>, fat hypercube (a hypercube with more than one processor at a node), or <a href="Mesh_networking" title="Mesh networking">n-dimensional mesh</a>.

Parallel computers based on interconnected networks need to have some kind of <a href="Routing" title="Routing">routing</a> to enable the passing of messages between nodes that are not directly connected. The medium used for communication between the processors is likely to be hierarchical in large multiprocessor machines.

<div class="mw-heading mw-heading3"><h3 id="Classes_of_parallel_computers">Classes of parallel computers</h3></div>

Parallel computers can be roughly classified according to the level at which the hardware supports parallelism. This classification is broadly analogous to the distance between basic computing nodes. These are not mutually exclusive; for example, clusters of symmetric multiprocessors are relatively common.

<div class="mw-heading mw-heading4"><h4 id="Multi-core_computing">Multi-core computing</h4></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Multi-core_processor" title="Multi-core processor">Multi-core processor</a></div>

A multi-core processor is a processor that includes multiple <a href="Central_processing_unit" title="Central processing unit">processing units</a> (called "cores") on the same chip. This processor differs from a <a href="Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> processor, which includes multiple <a href="Execution_unit" title="Execution unit">execution units</a> and can issue multiple instructions per clock cycle from one instruction stream (thread); in contrast, a multi-core processor can issue multiple instructions per clock cycle from multiple instruction streams. <a href="IBM" title="IBM">IBM</a>'s <a href="Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">Cell microprocessor</a>, designed for use in the <a href="Sony" title="Sony">Sony</a> <a href="PlayStation_3" title="PlayStation 3">PlayStation 3</a>, is a prominent multi-core processor. Each core in a multi-core processor can potentially be superscalar as well—that is, on every clock cycle, each core can issue multiple instructions from one thread.

<a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous multithreading</a> (of which Intel's <a href="Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a> is the best known) was an early form of pseudo-multi-coreism. A processor capable of concurrent multithreading includes multiple execution units in the same processing unit—that is it has a superscalar architecture—and can issue multiple instructions per clock cycle from multiple threads. <a href="Temporal_multithreading" title="Temporal multithreading">Temporal multithreading</a> on the other hand includes a single execution unit in the same processing unit and can issue one instruction at a time from multiple threads.

<div class="mw-heading mw-heading4"><h4 id="Symmetric_multiprocessing">Symmetric multiprocessing</h4></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">Symmetric multiprocessing</a></div>

A symmetric multiprocessor (SMP) is a computer system with multiple identical processors that share memory and connect via a <a href="Bus_(computing)" title="Bus (computing)">bus</a>.<a href="#cite_note-HP549-45">[45]</a> <a href="Bus_contention" title="Bus contention">Bus contention</a> prevents bus architectures from scaling. As a result, SMPs generally do not comprise more than 32 processors.<a href="#cite_note-46">[46]</a> Because of the small size of the processors and the significant reduction in the requirements for bus bandwidth achieved by large caches, such symmetric multiprocessors are extremely cost-effective, provided that a sufficient amount of memory bandwidth exists.<a href="#cite_note-HP549-45">[45]</a>

<div class="mw-heading mw-heading4"><h4 id="Distributed_computing">Distributed computing</h4></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Distributed_computing" title="Distributed computing">Distributed computing</a></div>

A distributed computer (also known as a distributed memory multiprocessor) is a distributed memory computer system in which the processing elements are connected by a network. Distributed computers are highly scalable. The terms "<a href="Concurrent_computing" title="Concurrent computing">concurrent computing</a>", "parallel computing", and "distributed computing" have a lot of overlap, and no clear distinction exists between them.<a href="#cite_note-47">[47]</a> The same system may be characterized both as "parallel" and "distributed"; the processors in a typical distributed system run concurrently in parallel.<a href="#cite_note-48">[48]</a>

<div class="mw-heading mw-heading5"><h5 id="Cluster_computing">Cluster computing</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Computer_cluster" title="Computer cluster">Computer cluster</a></div>

A cluster is a group of loosely coupled computers that work together closely, so that in some respects they can be regarded as a single computer.<a href="#cite_note-49">[49]</a> Clusters are composed of multiple standalone machines connected by a network. While machines in a cluster do not have to be symmetric, <a href="Load_balancing_(computing)" title="Load balancing (computing)">load balancing</a> is more difficult if they are not. The most common type of cluster is the <a href="Beowulf_(computing)" class="mw-redirect" title="Beowulf (computing)">Beowulf cluster</a>, which is a cluster implemented on multiple identical <a href="Commercial_off-the-shelf" title="Commercial off-the-shelf">commercial off-the-shelf</a> computers connected with a <a href="TCP/IP" class="mw-redirect" title="TCP/IP">TCP/IP</a> <a href="Ethernet" title="Ethernet">Ethernet</a> <a href="Local_area_network" title="Local area network">local area network</a>.<a href="#cite_note-50">[50]</a> Beowulf technology was originally developed by <a href="Thomas_Sterling_(computing)" title="Thomas Sterling (computing)">Thomas Sterling</a> and <a href="Donald_Becker" title="Donald Becker">Donald Becker</a>. 87% of all <a href="TOP500" title="TOP500">Top500</a> supercomputers are clusters.<a href="#cite_note-51">[51]</a> The remaining are Massively Parallel Processors, explained below.

Because grid computing systems (described below) can easily handle embarrassingly parallel problems, modern clusters are typically designed to handle more difficult problems—problems that require nodes to share intermediate results with each other more often. This requires a high bandwidth and, more importantly, a low-<a href="Latency_(engineering)" title="Latency (engineering)">latency</a> interconnection network. Many historic and current supercomputers use customized high-performance network hardware specifically designed for cluster computing, such as the Cray Gemini network.<a href="#cite_note-52">[52]</a> As of 2014, most current supercomputers use some off-the-shelf standard network hardware, often <a href="Myrinet" title="Myrinet">Myrinet</a>, <a href="InfiniBand" title="InfiniBand">InfiniBand</a>, or <a href="Gigabit_Ethernet" title="Gigabit Ethernet">Gigabit Ethernet</a>.

<div class="mw-heading mw-heading5"><h5 id="Massively_parallel_computing">Massively parallel computing</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Massively_parallel_(computing)" class="mw-redirect" title="Massively parallel (computing)">Massively parallel (computing)</a></div>

A massively parallel processor (MPP) is a single computer with many networked processors. MPPs have many of the same characteristics as clusters, but MPPs have specialized interconnect networks (whereas clusters use commodity hardware for networking). MPPs also tend to be larger than clusters, typically having "far more" than 100 processors.<a href="#cite_note-53">[53]</a> In an MPP, "each CPU contains its own memory and copy of the operating system and application. Each subsystem communicates with the others via a high-speed interconnect."<a href="#cite_note-54">[54]</a>

<a href="IBM" title="IBM">IBM</a>'s <a href="Blue_Gene" class="mw-redirect" title="Blue Gene">Blue Gene/L</a>, the fifth fastest <a href="Supercomputer" title="Supercomputer">supercomputer</a> in the world according to the June 2009 <a href="TOP500" title="TOP500">TOP500</a> ranking, is an MPP.

<div class="mw-heading mw-heading5"><h5 id="Grid_computing">Grid computing</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Grid_computing" title="Grid computing">Grid computing</a></div>

Grid computing is the most distributed form of parallel computing. It makes use of computers communicating over the <a href="Internet" title="Internet">Internet</a> to work on a given problem. Because of the low bandwidth and extremely high latency available on the Internet, distributed computing typically deals only with <a href="Embarrassingly_parallel" title="Embarrassingly parallel">embarrassingly parallel</a> problems.

Most grid computing applications use <a href="Middleware" title="Middleware">middleware</a> (software that sits between the operating system and the application to manage network resources and standardize the software interface). The most common grid computing middleware is the <a href="Berkeley_Open_Infrastructure_for_Network_Computing" title="Berkeley Open Infrastructure for Network Computing">Berkeley Open Infrastructure for Network Computing</a> (BOINC). Often <a href="Volunteer_computing" title="Volunteer computing">volunteer computing</a> software makes use of "spare cycles", performing computations at times when a computer is idling.<a href="#cite_note-55">[55]</a>

<div class="mw-heading mw-heading5"><h5 id="Cloud_computing">Cloud computing</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Cloud_computing" title="Cloud computing">Cloud computing</a></div>

The ubiquity of Internet brought the possibility of large-scale cloud computing.

<div class="mw-heading mw-heading4"><h4 id="Specialized_parallel_computers">Specialized parallel computers</h4></div>

Within parallel computing, there are specialized parallel devices that remain niche areas of interest. While not <a href="Domain-specific_programming_language" class="mw-redirect" title="Domain-specific programming language">domain-specific</a>, they tend to be applicable to only a few classes of parallel problems.

<div class="mw-heading mw-heading5"><h5 id="Reconfigurable_computing_with_field-programmable_gate_arrays">Reconfigurable computing with field-programmable gate arrays</h5></div>

<a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> is the use of a <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA) as a co-processor to a general-purpose computer. An FPGA is, in essence, a computer chip that can rewire itself for a given task.

FPGAs can be programmed with <a href="Hardware_description_language" title="Hardware description language">hardware description languages</a> such as <a href="VHDL" title="VHDL">VHDL</a><a href="#cite_note-56">[56]</a> or <a href="Verilog" title="Verilog">Verilog</a>.<a href="#cite_note-57">[57]</a> Several vendors have created <a href="C_to_HDL" title="C to HDL">C to HDL</a> languages that attempt to emulate the syntax and semantics of the <a href="C_programming_language" class="mw-redirect" title="C programming language">C programming language</a>, with which most programmers are familiar. The best known C to HDL languages are <a href="Mitrionics" title="Mitrionics">Mitrion-C</a>, <a href="Impulse_C" title="Impulse C">Impulse C</a>, and <a href="Handel-C" title="Handel-C">Handel-C</a>. Specific subsets of <a href="SystemC" title="SystemC">SystemC</a> based on C++ can also be used for this purpose.

AMD's decision to open its <a href="HyperTransport" title="HyperTransport">HyperTransport</a> technology to third-party vendors has become the enabling technology for high-performance reconfigurable computing.<a href="#cite_note-DAmour-58">[58]</a> According to Michael R. D'Amour, Chief Operating Officer of DRC Computer Corporation, "when we first walked into AMD, they called us 'the <a href="CPU_socket" title="CPU socket">socket</a> stealers.' Now they call us their partners."<a href="#cite_note-DAmour-58">[58]</a>

<div class="mw-heading mw-heading5"><h5 id="General-purpose_computing_on_graphics_processing_units_(GPGPU)">General-purpose computing on graphics processing units (GPGPU)</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="GPGPU" class="mw-redirect" title="GPGPU">GPGPU</a></div>

General-purpose computing on <a href="Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPGPU) is a fairly recent trend in computer engineering research. GPUs are co-processors that have been heavily optimized for <a href="Computer_graphics" title="Computer graphics">computer graphics</a> processing.<a href="#cite_note-59">[59]</a> Computer graphics processing is a field dominated by data parallel operations—particularly <a href="Linear_algebra" title="Linear algebra">linear algebra</a> <a href="Matrix_(mathematics)" title="Matrix (mathematics)">matrix</a> operations.

In the early days, GPGPU programs used the normal graphics APIs for executing programs. However, several new programming languages and platforms have been built to do general purpose computation on GPUs with both <a href="Nvidia" title="Nvidia">Nvidia</a> and <a href="AMD" title="AMD">AMD</a> releasing programming environments with <a href="CUDA" title="CUDA">CUDA</a> and <a href="AMD_FireStream#Software_Development_Kit" title="AMD FireStream">Stream SDK</a> respectively. Other GPU programming languages include <a href="BrookGPU" title="BrookGPU">BrookGPU</a>, <a href="PeakStream" class="mw-redirect" title="PeakStream">PeakStream</a>, and <a href="RapidMind" title="RapidMind">RapidMind</a>. Nvidia has also released specific products for computation in their <a href="Nvidia_Tesla" title="Nvidia Tesla">Tesla series</a>. The technology consortium Khronos Group has released the <a href="OpenCL" title="OpenCL">OpenCL</a> specification, which is a framework for writing programs that execute across platforms consisting of CPUs and GPUs. <a href="AMD" title="AMD">AMD</a>, <a href="Apple_Inc." title="Apple Inc.">Apple</a>, <a href="Intel" title="Intel">Intel</a>, <a href="Nvidia" title="Nvidia">Nvidia</a> and others are supporting <a href="OpenCL" title="OpenCL">OpenCL</a>.

<div class="mw-heading mw-heading5"><h5 id="Application-specific_integrated_circuits">Application-specific integrated circuits</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a></div>

Several <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> (ASIC) approaches have been devised for dealing with parallel applications.<a href="#cite_note-60">[60]</a><a href="#cite_note-61">[61]</a><a href="#cite_note-62">[62]</a>

Because an ASIC is (by definition) specific to a given application, it can be fully optimized for that application. As a result, for a given application, an ASIC tends to outperform a general-purpose computer. However, ASICs are created by <a href="Photolithography" title="Photolithography">UV photolithography</a>. This process requires a mask set, which can be extremely expensive. A mask set can cost over a million US dollars.<a href="#cite_note-63">[63]</a> (The smaller the transistors required for the chip, the more expensive the mask will be.) Meanwhile, performance increases in general-purpose computing over time (as described by <a href="Moore's_law" title="Moore's law">Moore's law</a>) tend to wipe out these gains in only one or two chip generations.<a href="#cite_note-DAmour-58">[58]</a> High initial cost, and the tendency to be overtaken by Moore's-law-driven general-purpose computing, has rendered ASICs unfeasible for most parallel computing applications. However, some have been built. One example is the PFLOPS <a href="RIKEN_MDGRAPE-3" title="RIKEN MDGRAPE-3">RIKEN MDGRAPE-3</a> machine which uses custom ASICs for <a href="Molecular_dynamics" title="Molecular dynamics">molecular dynamics</a> simulation.

<div class="mw-heading mw-heading5"><h5 id="Vector_processors">Vector processors</h5></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Vector_processor" title="Vector processor">Vector processor</a></div>

A vector processor is a CPU or computer system that can execute the same instruction on large sets of data. Vector processors have high-level operations that work on linear arrays of numbers or vectors. An example vector operation is A = B × C, where A, B, and C are each 64-element vectors of 64-bit <a href="Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> numbers.<a href="#cite_note-PH751-64">[64]</a> They are closely related to Flynn's SIMD classification.<a href="#cite_note-PH751-64">[64]</a>

<a href="Cray" title="Cray">Cray</a> computers became famous for their vector-processing computers in the 1970s and 1980s. However, vector processors—both as CPUs and as full computer systems—have generally disappeared. Modern <a href="Instruction_set" class="mw-redirect" title="Instruction set">processor instruction sets</a> do include some vector processing instructions, such as with <a href="Freescale_Semiconductor" title="Freescale Semiconductor">Freescale Semiconductor</a>'s <a href="AltiVec" title="AltiVec">AltiVec</a> and <a href="Intel" title="Intel">Intel</a>'s <a href="Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE).

<div class="mw-heading mw-heading2"><h2 id="Software">Software</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Parallel_programming_languages">Parallel programming languages</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="List_of_concurrent_and_parallel_programming_languages" title="List of concurrent and parallel programming languages">List of concurrent and parallel programming languages</a></div>

<a href="List_of_concurrent_and_parallel_programming_languages" title="List of concurrent and parallel programming languages">Concurrent programming languages</a>, <a href="Library_(computing)" title="Library (computing)">libraries</a>, <a href="Application_programming_interface" class="mw-redirect" title="Application programming interface">APIs</a>, and <a href="Parallel_programming_model" title="Parallel programming model">parallel programming models</a> (such as <a href="Algorithmic_skeleton" title="Algorithmic skeleton">algorithmic skeletons</a>) have been created for programming parallel computers. These can generally be divided into classes based on the assumptions they make about the underlying memory architecture—shared memory, distributed memory, or shared distributed memory. Shared memory programming languages communicate by manipulating shared memory variables. Distributed memory uses <a href="Message_passing" title="Message passing">message passing</a>. <a href="POSIX_Threads" class="mw-redirect" title="POSIX Threads">POSIX Threads</a> and <a href="OpenMP" title="OpenMP">OpenMP</a> are two of the most widely used shared memory APIs, whereas <a href="Message_Passing_Interface" title="Message Passing Interface">Message Passing Interface</a> (MPI) is the most widely used message-passing system API.<a href="#cite_note-65">[65]</a> One concept used in programming parallel programs is the <a href="Futures_and_promises" title="Futures and promises">future concept</a>, where one part of a program promises to deliver a required datum to another part of a program at some future time.

Efforts to standardize parallel programming include an open standard called <a href="OpenHMPP" title="OpenHMPP">OpenHMPP</a> for hybrid multi-core parallel programming. The OpenHMPP directive-based programming model offers a syntax to efficiently offload computations on hardware accelerators and to optimize data movement to/from the hardware memory using <a href="Remote_procedure_call" title="Remote procedure call">remote procedure calls</a>.

The rise of consumer GPUs has led to support for <a href="Compute_kernel" title="Compute kernel">compute kernels</a>, either in graphics APIs (referred to as <a href="Compute_shader" class="mw-redirect" title="Compute shader">compute shaders</a>), in dedicated APIs (such as <a href="OpenCL" title="OpenCL">OpenCL</a>), or in other language extensions.

<div class="mw-heading mw-heading3"><h3 id="Automatic_parallelization">Automatic parallelization</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Automatic_parallelization" title="Automatic parallelization">Automatic parallelization</a></div>

<a href="Automatic_parallelization" title="Automatic parallelization">Automatic parallelization</a> of a sequential program by a <a href="Compiler" title="Compiler">compiler</a> is the "holy grail" of parallel computing, especially with the aforementioned limit of processor frequency. Despite decades of work by compiler researchers, automatic parallelization has had only limited success.<a href="#cite_note-66">[66]</a>

Mainstream parallel programming languages remain either <a href="Explicit_parallelism" title="Explicit parallelism">explicitly parallel</a> or (at best) <a href="Implicit_parallelism" title="Implicit parallelism">partially implicit</a>, in which a programmer gives the compiler <a href="Directive_(programming)" title="Directive (programming)">directives</a> for parallelization. A few fully implicit parallel programming languages exist—<a href="SISAL" title="SISAL">SISAL</a>, Parallel <a href="Haskell" title="Haskell">Haskell</a>, <a href="SequenceL" title="SequenceL">SequenceL</a>, <a href="SystemC" title="SystemC">SystemC</a> (for <a href="Field-programmable_gate_array" title="Field-programmable gate array">FPGAs</a>), <a href="Mitrionics" title="Mitrionics">Mitrion-C</a>, <a href="VHDL" title="VHDL">VHDL</a>, and <a href="Verilog" title="Verilog">Verilog</a>.

<div class="mw-heading mw-heading3"><h3 id="Application_checkpointing">Application checkpointing</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Application_checkpointing" title="Application checkpointing">Application checkpointing</a></div>

As a computer system grows in complexity, the <a href="Mean_time_between_failures" title="Mean time between failures">mean time between failures</a> usually decreases. <a href="Application_checkpointing" title="Application checkpointing">Application checkpointing</a> is a technique whereby the computer system takes a "snapshot" of the application—a record of all current resource allocations and variable states, akin to a <a href="Core_dump" title="Core dump">core dump</a>—; this information can be used to restore the program if the computer should fail. Application checkpointing means that the program has to restart from only its last checkpoint rather than the beginning. While checkpointing provides benefits in a variety of situations, it is especially useful in highly parallel systems with a large number of processors used in <a href="High_performance_computing" class="mw-redirect" title="High performance computing">high performance computing</a>.<a href="#cite_note-67">[67]</a>

<div class="mw-heading mw-heading2"><h2 id="Algorithmic_methods">Algorithmic methods</h2></div>

As parallel computers become larger and faster, we are now able to solve problems that had previously taken too long to run. Fields as varied as <a href="Bioinformatics" title="Bioinformatics">bioinformatics</a> (for <a href="Protein_folding" title="Protein folding">protein folding</a> and <a href="Sequence_analysis" title="Sequence analysis">sequence analysis</a>) and economics have taken advantage of parallel computing. Common types of problems in parallel computing applications include:<a href="#cite_note-68">[68]</a>

<ul><li>Dense <a href="Linear_algebra" title="Linear algebra">linear algebra</a></li>

<li>Sparse linear algebra</li>

<li>Spectral methods (such as <a href="Cooley%E2%80%93Tukey_FFT_algorithm" title="Cooley–Tukey FFT algorithm">Cooley–Tukey fast Fourier transform</a>)</li>

<li><a href="N-body_problem" title="N-body problem">N-body problems</a> (such as <a href="Barnes%E2%80%93Hut_simulation" title="Barnes–Hut simulation">Barnes–Hut simulation</a>)</li>

<li><a href="Regular_grid" title="Regular grid">Structured grid</a> problems (such as <a href="Lattice_Boltzmann_methods" title="Lattice Boltzmann methods">Lattice Boltzmann methods</a>)</li>

<li><a href="Unstructured_grid" title="Unstructured grid">Unstructured grid</a> problems (such as found in <a href="Finite_element_analysis" class="mw-redirect" title="Finite element analysis">finite element analysis</a>)</li>

<li><a href="Monte_Carlo_method" title="Monte Carlo method">Monte Carlo method</a></li>

<li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a> (such as <a href="Brute_force_attack" class="mw-redirect" title="Brute force attack">brute-force cryptographic techniques</a>)</li>

<li><a href="Graph_traversal" title="Graph traversal">Graph traversal</a> (such as <a href="Sorting_algorithm" title="Sorting algorithm">sorting algorithms</a>)</li>

<li><a href="Dynamic_programming" title="Dynamic programming">Dynamic programming</a></li>

<li><a href="Branch_and_bound" title="Branch and bound">Branch and bound</a> methods</li>

<li><a href="Graphical_model" title="Graphical model">Graphical models</a> (such as detecting <a href="Hidden_Markov_model" title="Hidden Markov model">hidden Markov models</a> and constructing <a href="Bayesian_network" title="Bayesian network">Bayesian networks</a>)</li>

<li><a href="HBJ_model" title="HBJ model">HBJ model</a>, a concise message-passing model<a href="#cite_note-69">[69]</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a> simulation</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Fault_tolerance">Fault tolerance</h2></div>

<div role="note" class="hatnote navigation-not-searchable">Further information: <a href="Fault-tolerant_computer_system" class="mw-redirect" title="Fault-tolerant computer system">Fault-tolerant computer system</a></div>

Parallel computing can also be applied to the design of <a href="Fault-tolerant_computer_system" class="mw-redirect" title="Fault-tolerant computer system">fault-tolerant computer systems</a>, particularly via <a href="Lockstep_(computing)" title="Lockstep (computing)">lockstep</a> systems performing the same operation in parallel. This provides <a href="Redundancy_(engineering)" title="Redundancy (engineering)">redundancy</a> in case one component fails, and also allows automatic <a href="Error_detection" class="mw-redirect" title="Error detection">error detection</a> and <a href="Error_correction" class="mw-redirect" title="Error correction">error correction</a> if the results differ. These methods can be used to help prevent single-event upsets caused by transient errors.<a href="#cite_note-70">[70]</a> Although additional measures may be required in embedded or specialized systems, this method can provide a cost-effective approach to achieve n-modular redundancy in commercial off-the-shelf systems.

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<div role="note" class="hatnote navigation-not-searchable">For broader coverage of this topic, see <a href="History_of_computing" title="History of computing">History of computing</a>.</div>

The origins of true (MIMD) parallelism go back to <a href="Luigi_Federico_Menabrea" title="Luigi Federico Menabrea">Luigi Federico Menabrea</a> and his Sketch of the <a href="Analytic_Engine" class="mw-redirect" title="Analytic Engine">Analytic Engine</a> Invented by <a href="Charles_Babbage" title="Charles Babbage">Charles Babbage</a>.<a href="#cite_note-72">[72]</a><a href="#cite_note-PH753-73">[73]</a><a href="#cite_note-74">[74]</a>

In 1957, <a href="Compagnie_des_Machines_Bull" class="mw-redirect" title="Compagnie des Machines Bull">Compagnie des Machines Bull</a> announced the first computer architecture specifically designed for parallelism, the <a href="Bull_Gamma_60" title="Bull Gamma 60">Gamma 60</a>.<a href="#cite_note-75">[75]</a> It utilized a <a href="Fork%E2%80%93join_model" title="Fork–join model">fork-join model</a> and a "Program Distributor" to dispatch and collect data to and from independent processing units connected to a central memory.<a href="#cite_note-76">[76]</a><a href="#cite_note-77">[77]</a>

In April 1958, Stanley Gill (Ferranti) discussed parallel programming and the need for branching and waiting.<a href="#cite_note-78">[78]</a> Also in 1958, IBM researchers <a href="John_Cocke_(computer_scientist)" title="John Cocke (computer scientist)">John Cocke</a> and <a href="Daniel_Slotnick" title="Daniel Slotnick">Daniel Slotnick</a> discussed the use of parallelism in numerical calculations for the first time.<a href="#cite_note-G_Wilson-79">[79]</a> <a href="Burroughs_Corporation" title="Burroughs Corporation">Burroughs Corporation</a> introduced the D825 in 1962, a four-processor computer that accessed up to 16 memory modules through a <a href="Crossbar_switch" title="Crossbar switch">crossbar switch</a>.<a href="#cite_note-80">[80]</a> In 1967, Amdahl and Slotnick published a debate about the feasibility of parallel processing at American Federation of Information Processing Societies Conference.<a href="#cite_note-G_Wilson-79">[79]</a> It was during this debate that <a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a> was coined to define the limit of speed-up due to parallelism.

In 1969, <a href="Honeywell" title="Honeywell">Honeywell</a> introduced its first <a href="Multics" title="Multics">Multics</a> system, a symmetric multiprocessor system capable of running up to eight processors in parallel.<a href="#cite_note-G_Wilson-79">[79]</a> <a href="C.mmp" title="C.mmp">C.mmp</a>, a multi-processor project at <a href="Carnegie_Mellon_University" title="Carnegie Mellon University">Carnegie Mellon University</a> in the 1970s, was among the first multiprocessors with more than a few processors. The first bus-connected multiprocessor with snooping caches was the Synapse N+1 in 1984.<a href="#cite_note-PH753-73">[73]</a>

SIMD parallel computers can be traced back to the 1970s. The motivation behind early SIMD computers was to amortize the <a href="Propagation_delay" title="Propagation delay">gate delay</a> of the processor's <a href="Control_unit" title="Control unit">control unit</a> over multiple instructions.<a href="#cite_note-81">[81]</a> In 1964, Slotnick had proposed building a massively parallel computer for the <a href="Lawrence_Livermore_National_Laboratory" title="Lawrence Livermore National Laboratory">Lawrence Livermore National Laboratory</a>.<a href="#cite_note-G_Wilson-79">[79]</a> His design was funded by the <a href="US_Air_Force" class="mw-redirect" title="US Air Force">US Air Force</a>, which was the earliest SIMD parallel-computing effort, <a href="ILLIAC_IV" title="ILLIAC IV">ILLIAC IV</a>.<a href="#cite_note-G_Wilson-79">[79]</a> The key to its design was a fairly high parallelism, with up to 256 processors, which allowed the machine to work on large datasets in what would later be known as <a href="Vector_processor" title="Vector processor">vector processing</a>. However, ILLIAC IV was called "the most infamous of supercomputers", because the project was only one-fourth completed, but took 11 years and cost almost four times the original estimate.<a href="#cite_note-infamous-71">[71]</a> When it was finally ready to run its first real application in 1976, it was outperformed by existing commercial supercomputers such as the <a href="Cray-1" title="Cray-1">Cray-1</a>.

<div class="mw-heading mw-heading2"><h2 id="Biological_brain_as_massively_parallel_computer">Biological brain as massively parallel computer</h2></div>

In the early 1970s, at the <a href="MIT_Computer_Science_and_Artificial_Intelligence_Laboratory" title="MIT Computer Science and Artificial Intelligence Laboratory">MIT Computer Science and Artificial Intelligence Laboratory</a>, <a href="Marvin_Minsky" title="Marvin Minsky">Marvin Minsky</a> and <a href="Seymour_Papert" title="Seymour Papert">Seymour Papert</a> started developing the <a href="Society_of_Mind" title="Society of Mind">Society of Mind</a> theory, which views the biological brain as <a href="Massively_parallel" title="Massively parallel">massively parallel computer</a>. In 1986, Minsky published The Society of Mind, which claims that "mind is formed from many little agents, each mindless by itself".<a href="#cite_note-82">[82]</a> The theory attempts to explain how what we call intelligence could be a product of the interaction of non-intelligent parts. Minsky says that the biggest source of ideas about the theory came from his work in trying to create a machine that uses a robotic arm, a video camera, and a computer to build with children's blocks.<a href="#cite_note-83">[83]</a>

Similar models (which also view the biological brain as a massively parallel computer, i.e., the brain is made up of a constellation of independent or semi-independent agents) were also described by:

<ul><li>Thomas R. Blakeslee,<a href="#cite_note-84">[84]</a></li>

<li><a href="Michael_Gazzaniga" title="Michael Gazzaniga">Michael S. Gazzaniga</a>,<a href="#cite_note-85">[85]</a><a href="#cite_note-86">[86]</a></li>

<li><a href="Robert_E._Ornstein" title="Robert E. Ornstein">Robert E. Ornstein</a>,<a href="#cite_note-87">[87]</a></li>

<li><a href="Ernest_Hilgard" title="Ernest Hilgard">Ernest Hilgard</a>,<a href="#cite_note-88">[88]</a><a href="#cite_note-89">[89]</a></li>

<li><a href="Michio_Kaku" title="Michio Kaku">Michio Kaku</a>,<a href="#cite_note-90">[90]</a></li>

<li><a href="George_Gurdjieff" title="George Gurdjieff">George Ivanovich Gurdjieff</a>,<a href="#cite_note-91">[91]</a></li>

<li>Neurocluster Brain Model.<a href="#cite_note-92">[92]</a></li></ul>

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<ul><li><a href="Computer_multitasking" title="Computer multitasking">Computer multitasking</a></li>

<li><a href="Concurrency_(computer_science)" title="Concurrency (computer science)">Concurrency (computer science)</a></li>

<li><a href="Content_Addressable_Parallel_Processor" class="mw-redirect" title="Content Addressable Parallel Processor">Content Addressable Parallel Processor</a></li>

<li><a href="List_of_distributed_computing_conferences" title="List of distributed computing conferences">List of distributed computing conferences</a></li>

<li><a href="Loop-level_parallelism" title="Loop-level parallelism">Loop-level parallelism</a></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Manchester dataflow machine</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Parallel_programming_model" title="Parallel programming model">Parallel programming model</a></li>

<li><a href="Parallelization_contract" title="Parallelization contract">Parallelization contract</a></li>

<li><a href="Serializability" class="mw-redirect" title="Serializability">Serializability</a></li>

<li><a href="Synchronous_programming" class="mw-redirect" title="Synchronous programming">Synchronous programming</a></li>

<li><a href="Transputer" title="Transputer">Transputer</a></li>

<li><a href="Vector_processing" class="mw-redirect" title="Vector processing">Vector processing</a></li></ul>

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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-34"><a href="#cite_ref-34">^</a> Patterson and Hennessy, p. 748.

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<li id="cite_note-39"><a href="#cite_ref-39">^</a> Culler et al. p. 15.

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<li id="cite_note-Culler124-41"><a href="#cite_ref-Culler124_41-0">^</a> Culler et al. p. 124.

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<li id="cite_note-Culler125-42"><a href="#cite_ref-Culler125_42-0">^</a> Culler et al. p. 125.

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<li id="cite_note-PH713-44">^ <a href="#cite_ref-PH713_44-0">a</a> <a href="#cite_ref-PH713_44-1">b</a> Patterson and Hennessy, p. 713.

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<li id="cite_note-HP549-45">^ <a href="#cite_ref-HP549_45-0">a</a> <a href="#cite_ref-HP549_45-1">b</a> Hennessy and Patterson, p. 549.

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<li id="cite_note-46"><a href="#cite_ref-46">^</a> Patterson and Hennessy, p. 714.

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<li id="cite_note-PH751-64">^ <a href="#cite_ref-PH751_64-0">a</a> <a href="#cite_ref-PH751_64-1">b</a> Patterson and Hennessy, p. 751.

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<li id="cite_note-65"><a href="#cite_ref-65">^</a> The <a rel="nofollow" class="external text" href="http://awards.computer.org/ana/award/viewPastRecipients.action?id=16">Sidney Fernbach Award given to MPI inventor Bill Gropp</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110725191103/http://awards.computer.org/ana/award/viewPastRecipients.action?id=16">Archived</a> 2011-07-25 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a> refers to MPI as "the dominant HPC communications interface"

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<li id="cite_note-67"><a href="#cite_ref-67">^</a> Encyclopedia of Parallel Computing, Volume 4 by David Padua 2011 <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0387097651</bdi> page 265

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<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<ul><li><cite id="CITEREFRodriguezVillagraBaran2008" class="citation book cs1">Rodriguez, C.; Villagra, M.; Baran, B. (29 August 2008). "Asynchronous team algorithms for Boolean Satisfiability". 2007 2nd Bio-Inspired Models of Network, Information and Computing Systems. pp. 66–69. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FBIMNICS.2007.4610083">10.1109/BIMNICS.2007.4610083</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:15185219">15185219</a>.</cite></li>

<li>Sechin, A.; Parallel Computing in Photogrammetry. GIM International. #1, 2016, pp. 21–23.</li></ul>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<div class="side-box-text plainlist">Wikibooks has a book on the topic of: <a href="https://en.wikibooks.org/wiki/Distributed_Systems" class="extiw external" title="wikibooks:Distributed Systems">Distributed Systems</a></div></div>

</div>

<ul><li><a rel="nofollow" class="external text" href="http://www.llnl.gov/computing/tutorials/parallel_comp/">Lawrence Livermore National Laboratory: Introduction to Parallel Computing</a></li>

<li><a rel="nofollow" class="external text" href="http://www-unix.mcs.anl.gov/dbpp/">Designing and Building Parallel Programs, by Ian Foster</a></li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20021012122919/http://wotug.ukc.ac.uk/parallel/">Internet Parallel Computing Archive</a></li></ul>

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</style><div id="Parallel_computing346" style="font-size:114%;margin:0 4em"></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Distributed_computing" title="Distributed computing">Distributed computing</a></li>

<li><a href="Parallel_algorithm" title="Parallel algorithm">Parallel algorithm</a></li>

<li><a href="Massively_parallel" title="Massively parallel">Massively parallel</a></li>

<li><a href="Cloud_computing" title="Cloud computing">Cloud computing</a></li>

<li><a href="High-performance_computing" title="High-performance computing">High-performance computing</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore processor</a></li>

<li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>

<li><a href="Computer_network" title="Computer network">Computer network</a></li>

<li><a href="Systolic_array" title="Systolic array">Systolic array</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Levels</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Task_parallelism" title="Task parallelism">Thread</a></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Pipeline_(computing)" title="Pipeline (computing)">Pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> (SMT)</li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a> (SpMT)</li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Computer_multitasking#Cooperative_multitasking" title="Computer multitasking">Cooperative</a></li>

<li><a href="Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Clustered multi-thread</a> (CMT)</li>

<li><a href="Hardware_scout" title="Hardware scout">Hardware scout</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Theory</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Parallel_RAM" title="Parallel RAM">PRAM model</a></li>

<li><a href="Parallel_external_memory" title="Parallel external memory">PEM model</a></li>

<li><a href="Analysis_of_parallel_algorithms" title="Analysis of parallel algorithms">Analysis of parallel algorithms</a></li>

<li><a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a></li>

<li><a href="Gustafson's_law" title="Gustafson's law">Gustafson's law</a></li>

<li><a href="Cost_efficiency" title="Cost efficiency">Cost efficiency</a></li>

<li><a href="Karp%E2%80%93Flatt_metric" title="Karp–Flatt metric">Karp–Flatt metric</a></li>

<li><a href="Parallel_slowdown" title="Parallel slowdown">Slowdown</a></li>

<li><a href="Speedup" title="Speedup">Speedup</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Elements</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Process_(computing)" title="Process (computing)">Process</a></li>

<li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Fiber_(computer_science)" title="Fiber (computer science)">Fiber</a></li>

<li><a href="Instruction_window" title="Instruction window">Instruction window</a></li>

<li><a href="Array_(data_structure)" title="Array (data structure)">Array</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Coordination</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Memory_coherence" title="Memory coherence">Memory coherence</a></li>

<li><a href="Cache_coherence" title="Cache coherence">Cache coherence</a></li>

<li><a href="Cache_invalidation" title="Cache invalidation">Cache invalidation</a></li>

<li><a href="Barrier_(computer_science)" title="Barrier (computer science)">Barrier</a></li>

<li><a href="Synchronization_(computer_science)" title="Synchronization (computer science)">Synchronization</a></li>

<li><a href="Application_checkpointing" title="Application checkpointing">Application checkpointing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_programming" title="Computer programming">Programming</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Stream_processing" title="Stream processing">Stream processing</a></li>

<li><a href="Dataflow_programming" title="Dataflow programming">Dataflow programming</a></li>

<li><a href="Parallel_programming_model" title="Parallel programming model">Models</a>

<ul><li><a href="Implicit_parallelism" title="Implicit parallelism">Implicit parallelism</a></li>

<li><a href="Explicit_parallelism" title="Explicit parallelism">Explicit parallelism</a></li>

<li><a href="Concurrency_(computer_science)" title="Concurrency (computer science)">Concurrency</a></li></ul></li>

<li><a href="Non-blocking_algorithm" title="Non-blocking algorithm">Non-blocking algorithm</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_hardware" title="Computer hardware">Hardware</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a>

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing</a> (SIMT)</li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow architecture</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelined processor</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar processor</a></li>

<li><a href="Vector_processor" title="Vector processor">Vector processor</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessor</a>

<ul><li><a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric</a></li>

<li><a href="Asymmetric_multiprocessing" title="Asymmetric multiprocessing">asymmetric</a></li></ul></li>

<li><a href="Semiconductor_memory" title="Semiconductor memory">Memory</a>

<ul><li><a href="Shared_memory" title="Shared memory">shared</a></li>

<li><a href="Distributed_memory" title="Distributed memory">distributed</a></li>

<li><a href="Distributed_shared_memory" title="Distributed shared memory">distributed shared</a></li>

<li><a href="Massively_parallel" title="Massively parallel">Massively parallel</a> computer</li>

<li><a href="Computer_cluster" title="Computer cluster">Computer cluster</a>

<ul><li><a href="Beowulf_cluster" title="Beowulf cluster">Beowulf cluster</a></li></ul></li>

<li><a href="Grid_computing" title="Grid computing">Grid computer</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="API" title="API">APIs</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Ateji_PX" title="Ateji PX">Ateji PX</a></li>

<li><a href="Boost_(C%2B%2B_libraries)" title="Boost (C++ libraries)">Boost</a></li>

<li><a href="Chapel_(programming_language)" title="Chapel (programming language)">Chapel</a></li>

<li><a href="Charm%2B%2B" title="Charm++">Charm++</a></li>

<li><a href="Coarray_Fortran" title="Coarray Fortran">Coarray Fortran</a></li>

<li><a href="Dryad_(programming)" title="Dryad (programming)">Dryad</a></li>

<li><a href="Global_Arrays" title="Global Arrays">Global Arrays</a></li>

<li><a href="GPUOpen" title="GPUOpen">GPUOpen</a></li>

<li><a href="OpenMP" title="OpenMP">OpenMP</a></li>

<li><a href="OpenCL" title="OpenCL">OpenCL</a></li>

<li><a href="OpenHMPP" title="OpenHMPP">OpenHMPP</a></li>

<li><a href="OpenACC" title="OpenACC">OpenACC</a></li>

<li><a href="Parallel_Extensions" title="Parallel Extensions">Parallel Extensions</a></li>

<li><a href="Pthreads" title="Pthreads">pthreads</a></li>

<li><a href="RaftLib" title="RaftLib">RaftLib</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Problems</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Automatic_parallelization" title="Automatic parallelization">Automatic parallelization</a></li>

<li><a href="Deadlock_(computer_science)" title="Deadlock (computer science)">Deadlock</a></li>

<li><a href="Deterministic_algorithm" title="Deterministic algorithm">Deterministic algorithm</a></li>

<li><a href="Embarrassingly_parallel" title="Embarrassingly parallel">Embarrassingly parallel</a></li>

<li><a href="Parallel_slowdown" title="Parallel slowdown">Parallel slowdown</a></li>

<li><a href="Race_condition" title="Race condition">Race condition</a></li>

<li><a href="Software_lockout" title="Software lockout">Software lockout</a></li>

<li><a href="Scalability" title="Scalability">Scalability</a></li>

<li><a href="Starvation_(computer_science)" title="Starvation (computer science)">Starvation</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>

<ul><li> Category: Parallel computing</li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Programming_paradigms_(Comparison_by_language)368" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Programming_paradigms_(Comparison_by_language)368" style="font-size:114%;margin:0 4em"><a href="Programming_paradigm" title="Programming paradigm">Programming paradigms</a> (<a href="Comparison_of_multi-paradigm_programming_languages" title="Comparison of multi-paradigm programming languages">Comparison by language</a>)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Imperative_programming" title="Imperative programming">Imperative</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Structured_programming" title="Structured programming">Structured</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Jackson_structured_programming" title="Jackson structured programming">Jackson structures</a></li>

<li><a href="Block_(programming)" title="Block (programming)">Block-structured</a></li>

<li><a href="Modular_programming" title="Modular programming">Modular</a></li>

<li><a href="Non-structured_programming" title="Non-structured programming">Non-structured</a></li>

<li><a href="Procedural_programming" title="Procedural programming">Procedural</a></li>

<li><a href="Programming_in_the_large_and_programming_in_the_small" title="Programming in the large and programming in the small">Programming in the large and in the small</a></li>

<li><a href="Design_by_contract" title="Design by contract">Design by contract</a></li>

<li><a href="Invariant-based_programming" title="Invariant-based programming">Invariant-based</a></li>

<li><a href="Nested_function" title="Nested function">Nested function</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Object-oriented_programming" title="Object-oriented programming">Object-oriented</a> (<a href="Comparison_of_programming_languages_(object-oriented_programming)" title="Comparison of programming languages (object-oriented programming)">comparison</a>, <a href="List_of_object-oriented_programming_languages" title="List of object-oriented programming languages">list</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Class-based_programming" title="Class-based programming">Class-based</a>, <a href="Prototype-based_programming" title="Prototype-based programming">Prototype-based</a>, <a href="Object-based_language" title="Object-based language">Object-based</a></li>

<li><a href="Agent-oriented_programming" title="Agent-oriented programming">Agent</a></li>

<li><a href="Immutable_object" title="Immutable object">Immutable object</a></li>

<li><a href="Persistent_programming_language" title="Persistent programming language">Persistent</a></li>

<li><a href="Uniform_function_call_syntax" title="Uniform function call syntax">Uniform function call syntax</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Declarative_programming" title="Declarative programming">Declarative</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Functional_programming" title="Functional programming">Functional</a> (<a href="Comparison_of_functional_programming_languages" title="Comparison of functional programming languages">comparison</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Recursion_(computer_science)" title="Recursion (computer science)">Recursive</a></li>

<li><a href="Anonymous_function" title="Anonymous function">Anonymous function</a> (<a href="Partial_application" title="Partial application">Partial application</a>)</li>

<li><a href="Higher-order_programming" title="Higher-order programming">Higher-order</a></li>

<li><a href="Purely_functional_programming" title="Purely functional programming">Purely functional</a></li>

<li><a href="Total_functional_programming" title="Total functional programming">Total</a></li>

<li><a href="Strict_programming_language" title="Strict programming language">Strict</a></li>

<li><a href="Generalized_algebraic_data_type" title="Generalized algebraic data type">GADTs</a></li>

<li><a href="Dependent_type" title="Dependent type">Dependent types</a></li>

<li><a href="Functional_logic_programming" title="Functional logic programming">Functional logic</a></li>

<li><a href="Tacit_programming" title="Tacit programming">Point-free style</a></li>

<li><a href="Expression-oriented_programming_language" title="Expression-oriented programming language">Expression-oriented</a></li>

<li><a href="Applicative_programming_language" title="Applicative programming language">Applicative</a>, <a href="Concatenative_programming_language" title="Concatenative programming language">Concatenative</a></li>

<li><a href="Function-level_programming" title="Function-level programming">Function-level</a>, <a href="Value-level_programming" title="Value-level programming">Value-level</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Dataflow_programming" title="Dataflow programming">Dataflow</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Flow-based_programming" title="Flow-based programming">Flow-based</a></li>

<li><a href="Reactive_programming" title="Reactive programming">Reactive</a> (<a href="Functional_reactive_programming" title="Functional reactive programming">Functional reactive</a>)</li>

<li><a href="Signal_programming" class="mw-redirect" title="Signal programming">Signals</a></li>

<li><a href="Stream_processing" title="Stream processing">Streams</a></li>

<li><a href="Synchronous_programming_language" title="Synchronous programming language">Synchronous</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_programming" title="Logic programming">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abductive_logic_programming" title="Abductive logic programming">Abductive logic</a></li>

<li><a href="Answer_set_programming" title="Answer set programming">Answer set</a></li>

<li><a href="Constraint_programming" title="Constraint programming">Constraint</a> (<a href="Constraint_logic_programming" title="Constraint logic programming">Constraint logic</a>)</li>

<li><a href="Inductive_logic_programming" title="Inductive logic programming">Inductive logic</a></li>

<li><a href="Nondeterministic_programming" title="Nondeterministic programming">Nondeterministic</a></li>

<li><a href="Ontology_language" title="Ontology language">Ontology</a></li>

<li><a href="Probabilistic_logic_programming" title="Probabilistic logic programming">Probabilistic logic</a></li>

<li><a href="Query_language" title="Query language">Query</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Domain-specific_language" title="Domain-specific language">DSL</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Algebraic_modeling_language" title="Algebraic modeling language">Algebraic modeling</a></li>

<li><a href="Array_programming" title="Array programming">Array</a></li>

<li><a href="Automata-based_programming" title="Automata-based programming">Automata-based</a> (<a href="Action_language" title="Action language">Action</a>)</li>

<li><a href="Command_language" title="Command language">Command</a> (<a href="Spacecraft_command_language" title="Spacecraft command language">Spacecraft</a>)</li>

<li><a href="Differentiable_programming" title="Differentiable programming">Differentiable</a></li>

<li><a href="Grammar-oriented_programming" title="Grammar-oriented programming">Grammar-oriented</a></li>

<li><a href="Interface_description_language" title="Interface description language">Interface description</a></li>

<li><a href="Language-oriented_programming" title="Language-oriented programming">Language-oriented</a></li>

<li><a href="List_comprehension" title="List comprehension">List comprehension</a></li>

<li><a href="Modeling_language" title="Modeling language">Modeling</a></li>

<li><a href="Natural-language_programming" class="mw-redirect" title="Natural-language programming">Natural language</a></li>

<li><a href="Non-English-based_programming_languages" title="Non-English-based programming languages">Non-English-based</a></li>

<li><a href="Page_description_language" title="Page description language">Page description</a></li>

<li><a href="Pipeline_(software)" title="Pipeline (software)">Pipes</a> and <a href="Filter_(software)" title="Filter (software)">filters</a></li>

<li><a href="Probabilistic_programming" title="Probabilistic programming">Probabilistic</a></li>

<li><a href="Quantum_programming" title="Quantum programming">Quantum</a></li>

<li><a href="Scientific_programming_language" title="Scientific programming language">Scientific</a></li>

<li><a href="Scripting_language" title="Scripting language">Scripting</a></li>

<li><a href="Set_theoretic_programming" title="Set theoretic programming">Set-theoretic</a></li>

<li><a href="Simulation_language" title="Simulation language">Simulation</a></li>

<li><a href="Stack-oriented_programming" title="Stack-oriented programming">Stack-based</a></li>

<li><a href="System_programming_language" title="System programming language">System</a></li>

<li><a href="Tactile_programming_language" title="Tactile programming language">Tactile</a></li>

<li><a href="Template_processor" title="Template processor">Templating</a></li>

<li><a href="Transformation_language" title="Transformation language">Transformation</a> (<a href="Graph_rewriting" title="Graph rewriting">Graph rewriting</a>, <a href="Production_system_(computer_science)" title="Production system (computer science)">Production</a>, <a href="Pattern_matching" title="Pattern matching">Pattern</a>)</li>

<li><a href="Visual_programming_language" title="Visual programming language">Visual</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Concurrent_computing" title="Concurrent computing">Concurrent</a>, <a href="Distributed_computing" title="Distributed computing">distributed</a>, </th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Actor_model" title="Actor model">Actor-based</a></li>

<li><a href="Automatic_mutual_exclusion" title="Automatic mutual exclusion">Automatic mutual exclusion</a></li>

<li><a href="Choreographic_programming" title="Choreographic programming">Choreographic programming</a></li>

<li><a href="Concurrent_logic_programming" title="Concurrent logic programming">Concurrent logic</a> (<a href="Concurrent_constraint_logic_programming" title="Concurrent constraint logic programming">Concurrent constraint logic</a>)</li>

<li><a href="Concurrent_object-oriented_programming" title="Concurrent object-oriented programming">Concurrent OO</a></li>

<li><a href="Macroprogramming" title="Macroprogramming">Macroprogramming</a></li>

<li><a href="Multitier_programming" title="Multitier programming">Multitier programming</a></li>

<li><a href="Organic_computing" title="Organic computing">Organic computing</a></li>

<li><a href="Parallel_programming_model" title="Parallel programming model">Parallel programming models</a></li>

<li><a href="Partitioned_global_address_space" title="Partitioned global address space">Partitioned global address space</a></li>

<li><a href="Process-oriented_programming" title="Process-oriented programming">Process-oriented</a></li>

<li><a href="Relativistic_programming" title="Relativistic programming">Relativistic programming</a></li>

<li><a href="Service-oriented_programming" title="Service-oriented programming">Service-oriented</a></li>

<li><a href="Structured_concurrency" title="Structured concurrency">Structured concurrency</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Metaprogramming" title="Metaprogramming">Metaprogramming</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Attribute-oriented_programming" title="Attribute-oriented programming">Attribute-oriented</a></li>

<li><a href="Automatic_programming" title="Automatic programming">Automatic</a> (<a href="Inductive_programming" title="Inductive programming">Inductive</a>)</li>

<li><a href="Dynamic_programming_language" title="Dynamic programming language">Dynamic</a></li>

<li><a href="Extensible_programming" title="Extensible programming">Extensible</a></li>

<li><a href="Generic_programming" title="Generic programming">Generic</a></li>

<li><a href="Homoiconicity" title="Homoiconicity">Homoiconicity</a></li>

<li><a href="Interactive_programming" title="Interactive programming">Interactive</a></li>

<li><a href="Macro_(computer_science)" title="Macro (computer science)">Macro</a> (<a href="Hygienic_macro" title="Hygienic macro">Hygienic</a>)</li>

<li><a href="Metalinguistic_abstraction" title="Metalinguistic abstraction">Metalinguistic abstraction</a></li>

<li><a href="Multi-stage_programming" title="Multi-stage programming">Multi-stage</a></li>

<li><a href="Program_synthesis" title="Program synthesis">Program synthesis</a> (<a href="Bayesian_program_synthesis" title="Bayesian program synthesis">Bayesian</a>, <a href="Inferential_programming" title="Inferential programming">Inferential</a>, <a href="Programming_by_demonstration" title="Programming by demonstration">by demonstration</a>, <a href="Programming_by_example" title="Programming by example">by example</a>)</li>

<li><a href="Reflective_programming" title="Reflective programming">Reflective</a></li>

<li><a href="Self-modifying_code" title="Self-modifying code">Self-modifying code</a></li>

<li><a href="Symbolic_programming" title="Symbolic programming">Symbolic</a></li>

<li><a href="Template_metaprogramming" title="Template metaprogramming">Template</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Separation_of_concerns" title="Separation of concerns">Separation of concerns</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Aspect-oriented_programming" title="Aspect-oriented programming">Aspects</a></li>

<li><a href="Component-based_software_engineering" title="Component-based software engineering">Components</a></li>

<li><a href="Data-driven_programming" title="Data-driven programming">Data-driven</a></li>

<li><a href="Data-oriented_design" title="Data-oriented design">Data-oriented</a></li>

<li><a href="Event-driven_programming" title="Event-driven programming">Event-driven</a></li>

<li><a href="Feature-oriented_programming" title="Feature-oriented programming">Features</a></li>

<li><a href="Literate_programming" title="Literate programming">Literate</a></li>

<li><a href="Role-oriented_programming" title="Role-oriented programming">Roles</a></li>

<li><a href="Subject-oriented_programming" title="Subject-oriented programming">Subjects</a></li></ul>

</div></td></tr></tbody></table></div>

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